Features:
- Core
- • Ultra-high speed 32-bit 8051 Core with single clock per machine cycle (1T), about 70 times faster than traditional 8051.
- • 38 interrupt sources, 4 interrupt priority levels.
- • Supports online debugging and SWD hardware real-time emulation (P3.0/P3.1).
- Operating voltage
- • 1.9V ~ 5.5V (When operating temperature is below -40℃, operating voltage must not be lower than 3.0V).
- Operating temperature
- • -20℃ ~ +65℃ (Commercial Grade: internal high-speed IRC temp drift -0.76% ~ +0.98%).
- • -40℃ ~ +85℃ (Industrial Grade: internal high-speed IRC temp drift ±1.3%, operating frequency ≤ 42MHz).
- • -40℃ ~ +125℃ (Automotive Grade 1: internal high-speed IRC temp drift ±3%, operating frequency ≤ 33MHz).
- Flash memory
- • Up to 64 Kbytes of Flash program memory (ROM) used for storing user code.
- • Configurable EEPROM size, 512 bytes single page erased, repeatedly erased more than 100,000 times.
- • Supports hardware USB direct download and standard UART ISP download.
- SRAM
- • 2K bytes internal SRAM (edata).
- • 6K bytes internal extended RAM (internal xdata).
- • Usage Note: (Strongly recommend NOT using idata and pdata to declare variables).
- Clock control
- • Internal high-precision, high-stability high-speed IRC (42MHz and below, manually adjustable during ISP programming).
- • Internal 32KHz low speed IRC (without temperature/voltage compensation for low power, large error).
- • External crystal (42MHz and below) and external clock.
- • Internal PLL output clock (96MHz/144MHz, can independently serve as clock source for high-speed PWM and high-speed SPI).
- • Users can freely select from the above 4 clock sources.
- Reset
- • Hardware reset: Power-on reset (1.7V~1.9V), Reset pin reset (P5.4), Watchdog timer reset, Low Voltage Detection (LVD) reset (4 levels).
- • Software reset: Writing to reset trigger register via software.
- Interrupts
- • Provides 38 interrupt sources: INT0~INT4, Timers 0~4, USART1/2, UART3/4, ADC, LVD, SPI, I2C, Comparator, PWMA/B, CAN/CAN2, LIN, RTC, all I/O interrupts (4 groups), and multiple DMA interrupts.
- • Provides 4 interrupt priority levels.
- Digital peripherals
- • 5 16-bit timers (Timer0~Timer4).
- • 2 high-speed synchronous/asynchronous serial ports (USART1, USART2), 2 high-speed asynchronous serial ports (UART3, UART4).
- • 2 groups of advanced PWM (supports 8 channels with dead-time control).
- • SPI, I2C, I2S (Audio Bus), RTC (Real-Time Clock).
- • 2 independent CAN 2.0 control units, 1 independent LIN control unit (supports 1.3/2.1).
- • MDU32: Hardware 32-bit Multiplier and Divider.
- • DMA Module: Supports data transfer for SPI, I2C, UART1~4, ADC, LCD, and Memory-to-Memory.
- • Hardware Digital ID: Supports 32 bytes.
- Analog peripherals
- • ADC: 12-bit high-precision 10-channel ultra-high-speed ADC (includes 1 channel for testing internal 1.19V reference voltage).
- • Comparator: 1 set of voltage comparators.
- GPIO
- • Up to 19 GPIOs: P0.0~P0.3, P1.2~P1.7, P3.0~P3.7, P5.4.
- • Supports 4 modes: Quasi-bidirectional, Push-pull output, Open-drain, High-impedance input.
- • Except for P3.0 and P3.1, all other I/O pins default to high-impedance input state after power-on and must be configured before use.
- • Each I/O pin supports independent 10K internal pull-up and 10K pull-down resistors.
- Package
- • TSSOP20 (for STC32CL8K64-33A model).
Product Documents:
General Overview: STC32CL8K64 _Features.pdf
Data Sheet: STC32CL8K64.pdf
ROSH:
SCH/PCB: STC SCH/PCB library
Sample Code:
library Function: STC32G12K128 library function
Dome Code: STC32G12K128 Dome Code
STC32CL8K64 series Selection Table:
| MCU |
Operating voltage (V) |
Flash Code Memory (Byte) |
edata Internal extended DATA RAM which can be used as stack (Byte) |
xdata Internal extended SRAM (Byte) |
EEPROM (Byte) |
Maximum I/O Lines |
INT0 / INT1 / INT2 / INT3 / INT4 Interrupts (can wake-up CPU) |
All I/O ports support interrupts and can wake up MCU |
RTC Real-time Clock (Year / Month / Day / Hour / Min / Sec) |
DMA UART Asynchronous Serial Port (can wake-up CPU) |
DMA USART - LIN / SPI / IrDA (can wake-up CPU) |
Independent LIN Bus |
DMA SPI (can wake-up CPU) |
I2S Audio Bus |
CAN Bus |
DMA I2C (can wake-up CPU) |
MDU32 (Hardware 32-bit Multiplier and Divider) |
144MHz, 16-bit Advanced PWM Timer with Complementary Symmetrical Dead-time |
Timers / Counters (T0-T4 pin can wake-up CPU) |
Power-down Wake-up Timer |
DMA 10 channels High-speed ADC (8 PWMs can be used as 8 DACs) |
Comparator (May be used as ADC / external power-down detect) |
Internal LVD Interrupt (can wake-up CPU) |
Watch-dog Timer |
Internal High Reliable Reset Circuit (4 levels reset threshold) |
Internal High Precision Clock (Adjustable under 42MHz with frequency tracking) |
Clock Output and Reset |
Program Encrypted Transmission (Anti-blocking) |
Password can be set for next update |
Support RS485 Download |
Support Software/Hardware USB Direct Download |
Online Debug Itself |
| STC32CL8K48 |
1.9-5.5 |
48K |
2K |
6K |
16K |
17 |
Y |
Y |
Y |
2 |
2 |
1 |
Y |
Y |
2 |
Y |
Y |
5 |
8 |
Y |
12bit |
Y |
Y |
4-level |
Y |
Y |
Y |
Y |
Y |
Y |
Y |
Y |
| STC32CL8K64 |
1.9-5.5 |
64K |
2K |
6K |
IAP |
17 |
Y |
Y |
Y |
2 |
2 |
1 |
Y |
Y |
2 |
Y |
Y |
5 |
8 |
Y |
12bit |
Y |
Y |
4-level |
Y |
Y |
Y |
Y |
Y |
Y |
Y |
Y |
Sample & Buy:
Sample: Sample Request Form
Buy : Buy Online