STC8H3K64S2 series

Features:

Core

• Ultra-high speed 8051 Core with single clock per machine cycle, which is called 1T and the speed is about 12 times faster than traditional 8051

• Fully compatible instruction set with traditional 8051

• 19 interrupt sources and 4 interrupt priority levels

• Online debugging is supported

Operating voltage

• 1.9 to 5.5V

Operating temperature

• -40℃ ~ + 85℃(The chip is produced in -40℃～125℃ process. Please refer to the description of the electrical characteristics chapter for applications beyond the temperature range)

Flash memory

• Up to 64Kbytes of Flash memory to be used to store user code

• Configurable EEPROM size, 512bytes single page erased, can be repeatedly erased more than 100 thousand times.

• In-System-Programming, ISP in short, can be used to update the application code, no need for programmer.

• Online debugging with single chip is supported, and no emulator is needed. The number of breakpoints is unlimited theoretically.

SRAM

• 128 bytes internal direct access RAM (DATA, use keyword data to declare in C language program)

• 128 bytes internal indirect access RAM(IDATA, use keyword idata to declare in C language program)

• 3072 bytes internal extended RAM (internal XDATA, use keyword xdata to declare in C language program)

Clock

• Internal high precise RC clock IRC(IRC for short, ranges from 4MHz to 45MHz), adjustable while ISP and can be divided to lower frequency by user software, 100KHz for instance.

– Error:±0.3%

– -1.35%～+1.30% temperature drift (at the temperature range of -40°C to +85°C))

– -0.76%～+0.98% temperature drift (at the temperature range of -20℃ to 65℃)

• Internal 32KHz low speed IRC with large error

• External 4MHz~45MHz oscillator or external clock

• The three clock source above can be selected freely by used code.

Reset

• Hardware reset

– Power-on reset. (Effective when the chip does not enable the low voltage reset function)

– Reset by reset pin. The default function of P5.4 is the I/O port. The P5.4 pin can be set as the reset pin while ISP download. (Note: When the P5.4 pin is set as the reset pin, the reset level is low.)

– Watch dog timer reset

– Low voltage detection reset. 4 low voltage detection levels are provided, 2.0V, 2.4V, V2.7,V3.0

• Software reset

– Writing the reset trigger register using software

Interrupts

• 19 interrupt sources: INT0(Supports rising edge and falling edge interrupt), INT1(Supports rising edge and falling edge interrupt), INT2(Supports falling edge interrupt only), INT3(Supports falling edge interrupt only), INT4(Supports falling edge interrupt only), timer 0, timer 1, timer 2, timer 3, timer 4, UART 1, UART 2, ADC, LVD, SPI, I2C, comparator, PWMA, PWMB

• 4 interrupt priority levels

• Interrupts that can wake up the CPU in clock stop mode: INT0(P3.2), INT1(P3.3), INT2(P3.6), INT3(P3.7), INT4(P3.0), T0(P3.4), T1(P3.5), T2(P1.2), T3(P0.4), T4(P0.6), RXD(P3.0/P3.6/P1.6/P4.3), RXD2(P1.0/P4.6), I2C_SDA(P1.4/P2.4/P3.3), Comparator interrupt, LVD interrupt, Power-down wake-up timer.

Digital peripherals

• 5 16-bit timers: timer0, timer1, timer2, timer3, timer4, where the mode 3 of timer 0 has the Non-Maskable Interrupt (NMI in short) function. Mode 0 of timer 0 and timer 1 is 16-bit Auto-reload mode.

• 2 high speed UARTs: uart1, uart2, whose baud rate clock source may be fast as FOSC/4

• 8 channels/2 groups of enhanced PWMs, which can realize control signals with dead time, and support external fault detection function. In addition, it also supports 16-bit timers, 8 external interrupts, 8 external captures and pulse width measurement functions.

• SPI: Master mode, slave mode or master/slave automatic switch mode are supported.

• I2C: Master mode or slave mode are supported.

• MDU16: Hardware 16-bit Multiplier and Divider which supports 32-bit divided by 16-bit, 16-bit divided by 16-bit, 16-bit multiplied by 16-bit, data shift, and data normalization operations.

• I/O port interrupt: All I/Os support interrupts, each group of I/O interrupts has an independent interrupt entry address, all I/O interrupts can support 4 types interrupt mode: high level interrupt, low level interrupt, rising edge interrupt, falling edge interrupt. (Note: The I/O port interrupts of the STC8H3K64S2 series A version of the chip cannot wake up CPU from powerdown. The I/O port interrupts of the B version chip can wake up CPU from power-down, but only have one level of interrupt priority)

Analog peripherals

• Ultra high speed ADC which supports 12-bit precision 12 channels analog-to-digital convertor (channel 0 to channel 2, channel 6 to channel 14. No channel 3 and channel 5 because P1.3, P1.4 and P1.5 do not exist ). The maximum speed can be 800K(800K ADC conversions per second)

• Channel 15 of ADC is used to test the internal reference voltage. (The default internal reference voltage is 1.19V when the chip is shipped)

• A set of comparator (the CMP+ port and all ADC input ports can be selected as the positive terminal of the comparator, so the comparator can be used as a multi-channel comparator for time division multiplexing)

• DAC: 8 channels advanced PWMs timers can be used as 8 channels DAC

GPIO

• Up to 43 GPIOs: P0.0~P0.7, P1.0~P1.2, P1.6~P1.7, P2.0~P2.7, P3.0~P3.7, P4.0~P4.7, P5.0~P5.5

• 4 modes for all GPIOs: quasi-bidirectional mode, push-pull output mode, open drain mode, high-impedance input mode

• Except for P3.0 and P3.1, all other I/O ports are in a high-impedance state after power-on. User must set the I/O ports mode before using them. In addition, the internal 4K pull-up resistor of every I/O can be enabled independently.

Package

• LQFP48 , QFN48 , LQFP32 , QFN32 , TSSOP20